The present invention relates to interconnect metallization overlying a polymer layer and extending through vias in the polymer layer to underlying contact metallization.
High density interconnect (HDI) is a high performance chip packaging technology wherein sequential layers of metallization on polymer are used to interconnect chip pads with high chip density. In one form of HDI circuit module, an adhesive-coated polymer film overlay having via openings covers a plurality of integrated circuit chips in chip wells on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips through the vias. Methods for performing a HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. The polymer layer may comprise electrically insulating material upon which an electrically conductive material can adhere such as, for example, a polyimide.
Vias extending through the polymer layer to chip pads can be formed by any appropriate process. A preferred method of laser-drilling vias in the polymer film is described in Eichelberger et al., U.S. Pat. No. 4,894,115, issued Jan. 16, 1990. Conventional interconnect metallization processes generally use an argon ion laser to drill vias to chip pads or other types of contact metallization. Typical via depths are about thirty (30) to about forty (40) micrometers, and typical via sidewalls are sloped out and upwards from their horizontal bottom surfaces on the order of about forty-five degrees (45.degree.) to about sixty degrees (60.degree.). After via drilling, residual debris is removed by plasma ashing or reactive ion etching (RIE) treatment. The via surfaces can then be backsputtered to remove any oxide on the underlying metallization. A thin seed layer of titanium (about 1000 angstroms) is sputtered, and a thin layer of copper (about 3000 angstroms) is sputtered. These layers provide a thin conducting layer capable of serving as a ground plane for subsequent electrodeposition of copper. In one embodiment, copper is plated to a thickness of about four (4) micrometers, and another thin layer of titanium is then sputtered over the plated copper. The metallization layers (titanium, copper, copper, and titanium) are patterned using photoresist processing steps. Additional polymer layers can be applied with the via and via metallization process being repeated for each layer to complete the electrical circuit module.
Good coverage of the sputtered metal layers has been achieved using conventional methods because the sidewalls of the vias are sufficiently sloped. This technique, however, imposes limitations on the resolution capability for thicker polymer layers. For example, if a polymer layer is in the thickness range of fifty (50) to seventy-five (75) micrometers, if a slope of about forty-five degrees (45.degree.) to about sixty degrees (60.degree.) is to be used, the diameter of the hole at the top of the via will be significantly larger (twice as large) as the diameter for a dielectric layer having a thickness of thirty-five (35.degree.) micrometers, and the vias will thus require larger metal cover pads (areas of metallization in and around the vias).
Using current designs, vias often have twenty five micrometer (one mil) diameters at their narrowest sections and rectangular cover pads of about sixty-five micrometers per side. These dimensions cannot be achieved with thicker dielectric layers having the same sloped sidewalls, and interconnect density would thus be reduced for thicker polymer layers. Reductions in density lead to requirements for additional layers.
If steeper sidewalls (sidewalls with increasing slopes) are used, yield and reliability issues associated with metal coverage arise. Because sputtering is primarily directional, little or no metal is sputtered on very steep sidewalls of a polymer layer. Incomplete coverage of sputtered metal does not support subsequent electrodeposition processing, and metallized vias are formed with gaps in the metallization that can have high resistance values or create open circuits.